/*
 * ARM Limited (ARM) is supplying this software for use with Cortex-M
 * processor based microcontroller, but can be equally used for other
 * suitable processor architectures. This file can be freely distributed.
 * Modifications to this file shall be clearly marked.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 * @file     LKS32MC07x.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     10. January 2023
 * @note     Generated by SVDConv V3.3.39 on Tuesday, 10.01.2023 15:54:07
 *           from File 'LKS32MC07x.svd',
 *           last modified on Tuesday, 10.01.2023 07:53:57
 */



/** @addtogroup Linko Ltd.
  * @{
  */


/** @addtogroup LKS32MC07x
  * @{
  */


#ifndef LKS32MC07X_H
#define LKS32MC07X_H
#define LKS32MC07X

#include "basic.h"

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M0 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* =========================================  LKS32MC07x Specific Interrupt Numbers  ========================================= */
  TIMER0_IRQn               =   0,              /*!< 0  TIMER0                                                                 */
  TIMER1_IRQn               =   1,              /*!< 1  TIMER1                                                                 */
  TIMER2_IRQn               =   2,              /*!< 2  TIMER2                                                                 */
  TIMER3_IRQn               =   3,              /*!< 3  TIMER3                                                                 */
  
  QEP0_IRQn                 =   4,              /*!< 4  QEP0                                                                   */
  QEP1_IRQn                 =   5,              /*!< 5  QEP1                                                                   */
  I2C0_IRQn                 =   6,              /*!< 6  I2C0                                                                   */
  SPI0_IRQn                 =   7,              /*!< 7  SPI0                                                                   */
  
  GPIO_IRQn 				=   8,      		/*!< 8  SPI0                                                                   */
  HALL0_IRQn                =   9,              /*!< 9  HALL0                                                                  */
  UART0_IRQn                =  10,              /*!< 10 UART0                                                                  */
  UART1_IRQn                =  11,              /*!< 11 UART1                                                                  */
  
  DSP0_IRQn                 =  12,              /*!< 12 DSP0                                                                   */
  CMP_IRQn                  =  13,              /*!< 12 CMP                                                                    */
  ADC0_IRQn                 =  14,              /*!< 14 ADC0                                                                   */
  ADC1_IRQn                 =  15,              /*!< 15 ADC1                                                                   */
  
  MCPWM0_IRQn               =  16,              /*!< 16 MCPWM0                                                                 */
  MCPWM1_IRQn               =  17,              /*!< 17 MCPWM1                                                                 */
  DMA0_IRQn                 =  18,              /*!< 18 DMA0                                                                   */
  CAN0_IRQn                 =  19,              /*!< 19 CAN0                                                                   */
  
  SIF0_IRQn                 =  20,              /*!< 20 SIF0                                                                   */
  WAKE_IRQn                 =  21,              /*!< 21 WAKE                                                                   */
  SW_IRQn                   =  22,              /*!< 22 SW                                                                     */
  PWRDN_IRQn                =  23,              /*!< 23 PWRDN                                                                  */
  
  CL0_IRQn                  =  24               /*!< 24 CL0                                                                    */
} IRQn_Type;

#ifndef __CM0_REV
  #define __CM0_REV                 0x0100U       /*!< CM0 Core Revision                                                         */
#endif

#ifndef __Vendor_SysTickConfig
  #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#endif


#ifndef __NVIC_PRIO_BITS
  #define __NVIC_PRIO_BITS    2               /*!< standard definition for NVIC Priority Bits */
#endif

//-----------------------------------------------------------

#define SYS_BASE                    0x40000000UL
#define FLASH_BASE                  0x00020000UL
#define SPI0_BASE                   0x40010000UL
#define I2C0_BASE                   0x40010100UL
#define CMP_BASE                    0x40010200UL
#define HALL0_BASE                  0x40010300UL
#define ADC0_BASE                   0x40010400UL
#define ADC1_BASE                   0x40010500UL
#define TIMER0_BASE                 0x40010600UL
#define TIMER1_BASE                 0x40010700UL
#define TIMER2_BASE                 0x40010800UL
#define TIMER3_BASE                 0x40010900UL
#define QEP0_BASE                   0x40010A00UL
#define QEP1_BASE                   0x40010B00UL
#define MCPWM0_BASE                 0x40010C00UL
#define GPIO0_BASE                  0x40010D00UL
#define GPIO1_BASE                  0x40010D40UL
#define GPIO2_BASE                  0x40010D80UL
#define GPIO3_BASE                  0x40010DC0UL
#define EXTI_BASE                   0x40010E00UL
#define CRC0_BASE                   0x40010F00UL
#define UART0_BASE                  0x40011000UL
#define UART1_BASE                  0x40011100UL
#define DMA0_BASE                   0x40011200UL
#define CAN0_BASE                   0x40011300UL
#define SIF0_BASE                   0x40011500UL
#define DSP0_BASE                   0x40012000UL
#define DSP0_REG_BASE       		0x40013000UL
#define IWDG_BASE                   0x40011700UL
#define AON_BASE                    0x40011720UL
#define CL0_BASE                    0x40011800UL

#define SYS_AFE_ADC         REG32(SYS_BASE + 0x00) 
#define SYS_AFE_INFO        REG32(SYS_BASE + 0x04) 
#define SYS_AFE_DBG         REG32(SYS_BASE + 0x08) 

#define SYS_AFE_REG0        REG32(SYS_BASE + 0x10) 
#define SYS_AFE_REG1        REG32(SYS_BASE + 0x14)  
#define SYS_AFE_REG2        REG32(SYS_BASE + 0x18)  
#define SYS_AFE_REG3        REG32(SYS_BASE + 0x1C)  
#define SYS_AFE_REG4        REG32(SYS_BASE + 0x20)  
#define SYS_AFE_REG5        REG32(SYS_BASE + 0x24)  
#define SYS_AFE_REG6        REG32(SYS_BASE + 0x28)  
#define SYS_AFE_REG7        REG32(SYS_BASE + 0x2C)  
#define SYS_AFE_REG8        REG32(SYS_BASE + 0x30)  
#define SYS_AFE_REG9        REG32(SYS_BASE + 0x34)  
#define SYS_AFE_REGA        REG32(SYS_BASE + 0x38)  
#define SYS_AFE_REGB        REG32(SYS_BASE + 0x3C)  
#define SYS_AFE_REGC        REG32(SYS_BASE + 0x40)

#define SYS_AFE_DAC_CTRL    REG32(SYS_BASE + 0x5C)  
#define SYS_AFE_DAC0        REG32(SYS_BASE + 0x60)  
#define SYS_AFE_DAC1        REG32(SYS_BASE + 0x64)  
#define SYS_AFE_DAC0_AMC    REG32(SYS_BASE + 0x68)  
#define SYS_AFE_DAC0_DC     REG32(SYS_BASE + 0x6C)  
#define SYS_AFE_DAC1_AMC    REG32(SYS_BASE + 0x70)  
#define SYS_AFE_DAC1_DC     REG32(SYS_BASE + 0x74)  

#define SYS_CLK_CFG         REG32(SYS_BASE + 0x80)  
#define SYS_IO_CFG          REG32(SYS_BASE + 0x84)  
#define SYS_DBG_CFG         REG32(SYS_BASE + 0x88)  

#define SYS_CLK_DIV0        REG32(SYS_BASE + 0x90)  // SPI clock div
#define SYS_CLK_DIV1        REG32(SYS_BASE + 0x94)  // I2C clock div
#define SYS_CLK_DIV2        REG32(SYS_BASE + 0x98)  // UART0/1 clock div
#define SYS_CLK_FEN         REG32(SYS_BASE + 0x9C)  // perapheral clock enable
#define SYS_TRIM            REG32(SYS_BASE + 0xA0)  
#define SYS_SFT_RST         REG32(SYS_BASE + 0xA4)  
#define SYS_WR_PROTECT      REG32(SYS_BASE + 0xA8)
#define SYS_PROTECT         REG32(SYS_BASE + 0xA8)
//#define SYS_PROT            REG32(SYS_BASE + 0xA8)
#define SYS_MBIST           REG32(SYS_BASE + 0xC0)
#define SYS_FLSE            REG32(SYS_BASE + 0xD0)
#define SYS_FLSP            REG32(SYS_BASE + 0xD4)
#define SYS_FLST            REG32(SYS_BASE + 0xD8)
#define SYS_SBIST           REG32(SYS_BASE + 0xE0)
#define SYS_TEST            REG32(SYS_BASE + 0xFC)

#define PSW_SYS_CLR_RST     0xCA40
#define PSW_SYS_SET_IAP     0x3720 // lsb must be ZERO
#define PSW_SYS_PROTECT     0x7a83
#define PSW_PROTECT         0x7a83
#define PSW_PROT            0x7a83

#define FLASH_PASSEN       0xB714AD9C
#define FLASH_PASS_NVR_EN  0x7531FDB9
#define FLASH_PASS_PROG    0x2468ACE0
#define FLASH_PASS_ERASE   0x7654DCBA
#define FLASH_PASS_CONFEN  0x13579BDF

#define FLASH_CFG           REG32(FLASH_BASE + 0x00)
#define FLASH_ADDR          REG32(FLASH_BASE + 0x04) 
#define FLASH_WDATA         REG32(FLASH_BASE + 0x08)
#define FLASH_RDATA         REG32(FLASH_BASE + 0x0C)
#define FLASH_ERASE         REG32(FLASH_BASE + 0x10)
#define FLASH_PROTECT       REG32(FLASH_BASE + 0x14)
#define FLASH_READY         REG32(FLASH_BASE + 0x18)
#define FLASH_SIZE          REG32(FLASH_BASE + 0x1C)
#define FLASH_NCFG          REG32(FLASH_BASE + 0x20)
#define FLASH_NADDR         REG32(FLASH_BASE + 0x24) 
#define FLASH_NWDATA        REG32(FLASH_BASE + 0x28)
#define FLASH_NRDATA        REG32(FLASH_BASE + 0x2C)
#define FLASH_NERASE        REG32(FLASH_BASE + 0x30)
#define FLASH_NPROTECT      REG32(FLASH_BASE + 0x34)
#define FLASH_NKEY			REG32(FLASH_BASE + 0x34)

#define SPI0_CFG            REG32(SPI0_BASE + 0x00)
#define SPI0_IE             REG32(SPI0_BASE + 0x04)
#define SPI0_DIV            REG32(SPI0_BASE + 0x08)
#define SPI0_BAUD			REG32(SPI0_BASE + 0x08)
#define SPI0_TX_DATA        REG32(SPI0_BASE + 0x0C)
#define SPI0_TXDATA			REG32(SPI0_BASE + 0x0C)
#define SPI0_RX_DATA        REG32(SPI0_BASE + 0x10)
#define SPI0_RXDATA			REG32(SPI0_BASE + 0x10)
#define SPI0_SIZE           REG32(SPI0_BASE + 0x14)

#define I2C0_ADDR 	        REG32(I2C0_BASE + 0x00) 
#define I2C0_CFG 	        REG32(I2C0_BASE + 0x04)
#define I2C0_SCR 	        REG32(I2C0_BASE + 0x08)
#define I2C0_DATA 	        REG32(I2C0_BASE + 0x0C)
#define I2C0_MSCR 	        REG32(I2C0_BASE + 0x10)
#define I2C0_BCR            REG32(I2C0_BASE + 0x14)

#define CMP_IE              REG32(CMP_BASE + 0x00)
#define CMP_IF              REG32(CMP_BASE + 0x04)
#define CMP_TCLK            REG32(CMP_BASE + 0x08)
#define CMP_CFG             REG32(CMP_BASE + 0x0C)
#define CMP_BLCWIN          REG32(CMP_BASE + 0x10)
#define CMP_DATA            REG32(CMP_BASE + 0x14)

#define HALL0_CFG           REG32(HALL0_BASE + 0x00) 
#define HALL0_INFO          REG32(HALL0_BASE + 0x04) 
#define HALL0_WIDTH         REG32(HALL0_BASE + 0x08) 
#define HALL0_TH            REG32(HALL0_BASE + 0x0C)
#define HALL0_CNT           REG32(HALL0_BASE + 0x10) 

#define ADC0_DAT0           REG32(ADC0_BASE + 0x00)
#define ADC0_DAT1           REG32(ADC0_BASE + 0x04)
#define ADC0_DAT2           REG32(ADC0_BASE + 0x08)
#define ADC0_DAT3           REG32(ADC0_BASE + 0x0C)
#define ADC0_DAT4           REG32(ADC0_BASE + 0x10)
#define ADC0_DAT5           REG32(ADC0_BASE + 0x14)
#define ADC0_DAT6           REG32(ADC0_BASE + 0x18)
#define ADC0_DAT7           REG32(ADC0_BASE + 0x1C)
#define ADC0_DAT8           REG32(ADC0_BASE + 0x20)
#define ADC0_DAT9           REG32(ADC0_BASE + 0x24)
#define ADC0_DAT10          REG32(ADC0_BASE + 0x28)
#define ADC0_DAT11          REG32(ADC0_BASE + 0x2C)
#define ADC0_DAT12          REG32(ADC0_BASE + 0x30)
#define ADC0_DAT13          REG32(ADC0_BASE + 0x34)
#define ADC0_IDAT0          REG32(ADC0_BASE + 0x38)
#define ADC0_IDAT1          REG32(ADC0_BASE + 0x3C)
#define ADC0_ICHN           REG32(ADC0_BASE + 0x40)

#define ADC0_CHN0           REG32(ADC0_BASE + 0x50)
#define ADC0_CHN1           REG32(ADC0_BASE + 0x54)
#define ADC0_CHN2           REG32(ADC0_BASE + 0x58)
#define ADC0_CHN3           REG32(ADC0_BASE + 0x5C)
#define ADC0_CHNT           REG32(ADC0_BASE + 0x60)
#define ADC0_GAIN           REG32(ADC0_BASE + 0x64)
#define ADC0_CFG            REG32(ADC0_BASE + 0x74)
#define ADC0_TRIG           REG32(ADC0_BASE + 0x78)
#define ADC0_SWT            REG32(ADC0_BASE + 0x7C)

#define ADC0_DC0            REG32(ADC0_BASE + 0x80)
#define ADC0_AMC0           REG32(ADC0_BASE + 0x84)
#define ADC0_DC1            REG32(ADC0_BASE + 0x88)
#define ADC0_AMC1           REG32(ADC0_BASE + 0x8C)
#define ADC0_IE             REG32(ADC0_BASE + 0x90)
#define ADC0_IF             REG32(ADC0_BASE + 0x94)
#define ADC0_LTH            REG32(ADC0_BASE + 0xC4)
#define ADC0_HTH            REG32(ADC0_BASE + 0xC8)
#define ADC0_GEN            REG32(ADC0_BASE + 0xCC)

#define ADC1_DAT0           REG32(ADC1_BASE + 0x00)
#define ADC1_DAT1           REG32(ADC1_BASE + 0x04)
#define ADC1_DAT2           REG32(ADC1_BASE + 0x08)
#define ADC1_DAT3           REG32(ADC1_BASE + 0x0C)
#define ADC1_DAT4           REG32(ADC1_BASE + 0x10)
#define ADC1_DAT5           REG32(ADC1_BASE + 0x14)
#define ADC1_DAT6           REG32(ADC1_BASE + 0x18)
#define ADC1_DAT7           REG32(ADC1_BASE + 0x1C)
#define ADC1_DAT8           REG32(ADC1_BASE + 0x20)
#define ADC1_DAT9           REG32(ADC1_BASE + 0x24)
#define ADC1_DAT10          REG32(ADC1_BASE + 0x28)
#define ADC1_DAT11          REG32(ADC1_BASE + 0x2C)
#define ADC1_DAT12          REG32(ADC1_BASE + 0x30)
#define ADC1_DAT13          REG32(ADC1_BASE + 0x34)
#define ADC1_IDAT0          REG32(ADC1_BASE + 0x38)
#define ADC1_IDAT1          REG32(ADC1_BASE + 0x3C)
#define ADC1_ICHN           REG32(ADC1_BASE + 0x40)

#define ADC1_CHN0           REG32(ADC1_BASE + 0x50)
#define ADC1_CHN1           REG32(ADC1_BASE + 0x54)
#define ADC1_CHN2           REG32(ADC1_BASE + 0x58)
#define ADC1_CHN3           REG32(ADC1_BASE + 0x5C)
#define ADC1_CHNT           REG32(ADC1_BASE + 0x60)
#define ADC1_GAIN           REG32(ADC1_BASE + 0x64)
#define ADC1_CFG            REG32(ADC1_BASE + 0x74)
#define ADC1_TRIG           REG32(ADC1_BASE + 0x78)
#define ADC1_SWT            REG32(ADC1_BASE + 0x7C)

#define ADC1_DC0            REG32(ADC1_BASE + 0x80)
#define ADC1_AMC0           REG32(ADC1_BASE + 0x84)
#define ADC1_DC1            REG32(ADC1_BASE + 0x88)
#define ADC1_AMC1           REG32(ADC1_BASE + 0x8C)
#define ADC1_IE             REG32(ADC1_BASE + 0x90)
#define ADC1_IF             REG32(ADC1_BASE + 0x94)
#define ADC1_LTH            REG32(ADC1_BASE + 0xC4)
#define ADC1_HTH            REG32(ADC1_BASE + 0xC8)
#define ADC1_GEN            REG32(ADC1_BASE + 0xCC)

#define UTIMER0_CFG         REG32(TIMER0_BASE + 0x00)
#define UTIMER0_TH          REG32(TIMER0_BASE + 0x04)
#define UTIMER0_CNT         REG32(TIMER0_BASE + 0x08)
#define UTIMER0_CMP0        REG32(TIMER0_BASE + 0x0C)
#define UTIMER0_CMP1        REG32(TIMER0_BASE + 0x10)
#define UTIMER0_EVT         REG32(TIMER0_BASE + 0x14)
#define UTIMER0_FLT         REG32(TIMER0_BASE + 0x18)
#define UTIMER0_IE          REG32(TIMER0_BASE + 0x1C)
#define UTIMER0_IF          REG32(TIMER0_BASE + 0x20)
#define UTIMER0_IO          REG32(TIMER0_BASE + 0x24)

#define TIMER0_CFG         REG32(TIMER0_BASE + 0x00)
#define TIMER0_TH          REG32(TIMER0_BASE + 0x04)
#define TIMER0_CNT         REG32(TIMER0_BASE + 0x08)
#define TIMER0_CMP0        REG32(TIMER0_BASE + 0x0C)
#define TIMER0_CMP1        REG32(TIMER0_BASE + 0x10)
#define TIMER0_EVT         REG32(TIMER0_BASE + 0x14)
#define TIMER0_FLT         REG32(TIMER0_BASE + 0x18)
#define TIMER0_IE          REG32(TIMER0_BASE + 0x1C)
#define TIMER0_IF          REG32(TIMER0_BASE + 0x20)
#define TIMER0_IO          REG32(TIMER0_BASE + 0x24)

#define UTIMER1_CFG         REG32(TIMER1_BASE + 0x00)
#define UTIMER1_TH          REG32(TIMER1_BASE + 0x04)
#define UTIMER1_CNT         REG32(TIMER1_BASE + 0x08)
#define UTIMER1_CMP0        REG32(TIMER1_BASE + 0x0C)
#define UTIMER1_CMP1        REG32(TIMER1_BASE + 0x10)
#define UTIMER1_EVT         REG32(TIMER1_BASE + 0x14)
#define UTIMER1_FLT         REG32(TIMER1_BASE + 0x18)
#define UTIMER1_IE          REG32(TIMER1_BASE + 0x1C)
#define UTIMER1_IF          REG32(TIMER1_BASE + 0x20)

#define TIMER1_CFG          REG32(TIMER1_BASE + 0x00)
#define TIMER1_TH           REG32(TIMER1_BASE + 0x04)
#define TIMER1_CNT          REG32(TIMER1_BASE + 0x08)
#define TIMER1_CMP0         REG32(TIMER1_BASE + 0x0C)
#define TIMER1_CMP1         REG32(TIMER1_BASE + 0x10)
#define TIMER1_EVT          REG32(TIMER1_BASE + 0x14)
#define TIMER1_FLT          REG32(TIMER1_BASE + 0x18)
#define TIMER1_IE           REG32(TIMER1_BASE + 0x1C)
#define TIMER1_IF           REG32(TIMER1_BASE + 0x20)

#define UTIMER2_CFG         REG32(TIMER2_BASE + 0x00)
#define UTIMER2_TH          REG32(TIMER2_BASE + 0x04)
#define UTIMER2_CNT         REG32(TIMER2_BASE + 0x08)
#define UTIMER2_CMP0        REG32(TIMER2_BASE + 0x0C)
#define UTIMER2_CMP1        REG32(TIMER2_BASE + 0x10)
#define UTIMER2_EVT         REG32(TIMER2_BASE + 0x14)
#define UTIMER2_FLT         REG32(TIMER2_BASE + 0x18)
#define UTIMER2_IE          REG32(TIMER2_BASE + 0x1C)
#define UTIMER2_IF          REG32(TIMER2_BASE + 0x20)

#define TIMER2_CFG          REG32(TIMER2_BASE + 0x00)
#define TIMER2_TH           REG32(TIMER2_BASE + 0x04)
#define TIMER2_CNT          REG32(TIMER2_BASE + 0x08)
#define TIMER2_CMP0         REG32(TIMER2_BASE + 0x0C)
#define TIMER2_CMP1         REG32(TIMER2_BASE + 0x10)
#define TIMER2_EVT          REG32(TIMER2_BASE + 0x14)
#define TIMER2_FLT          REG32(TIMER2_BASE + 0x18)
#define TIMER2_IE           REG32(TIMER2_BASE + 0x1C)
#define TIMER2_IF           REG32(TIMER2_BASE + 0x20)

#define UTIMER3_CFG         REG32(TIMER3_BASE + 0x00)
#define UTIMER3_TH          REG32(TIMER3_BASE + 0x04)
#define UTIMER3_CNT         REG32(TIMER3_BASE + 0x08)
#define UTIMER3_CMP0        REG32(TIMER3_BASE + 0x0C)
#define UTIMER3_CMP1        REG32(TIMER3_BASE + 0x10)
#define UTIMER3_EVT         REG32(TIMER3_BASE + 0x14)
#define UTIMER3_FLT         REG32(TIMER3_BASE + 0x18)
#define UTIMER3_IE          REG32(TIMER3_BASE + 0x1C)
#define UTIMER3_IF          REG32(TIMER3_BASE + 0x20)

#define TIMER3_CFG          REG32(TIMER3_BASE + 0x00)
#define TIMER3_TH           REG32(TIMER3_BASE + 0x04)
#define TIMER3_CNT          REG32(TIMER3_BASE + 0x08)
#define TIMER3_CMP0         REG32(TIMER3_BASE + 0x0C)
#define TIMER3_CMP1         REG32(TIMER3_BASE + 0x10)
#define TIMER3_EVT          REG32(TIMER3_BASE + 0x14)
#define TIMER3_FLT          REG32(TIMER3_BASE + 0x18)
#define TIMER3_IE           REG32(TIMER3_BASE + 0x1C)
#define TIMER3_IF           REG32(TIMER3_BASE + 0x20)



#define QEP0_CFG            REG32(QEP0_BASE + 0x00)
#define QEP0_TH             REG32(QEP0_BASE + 0x04)
#define QEP0_CNT            REG32(QEP0_BASE + 0x08)
#define QEP0_IE             REG32(QEP0_BASE + 0x0C)
#define QEP0_IF             REG32(QEP0_BASE + 0x10)

#define QEP1_CFG            REG32(QEP1_BASE + 0x00)
#define QEP1_TH             REG32(QEP1_BASE + 0x04)
#define QEP1_CNT            REG32(QEP1_BASE + 0x08)
#define QEP1_IE             REG32(QEP1_BASE + 0x0C)
#define QEP1_IF             REG32(QEP1_BASE + 0x10)



#define MCPWM0_TH00        REG32(MCPWM0_BASE + 0x00) 
#define MCPWM0_TH01        REG32(MCPWM0_BASE + 0x04)
#define MCPWM0_TH10        REG32(MCPWM0_BASE + 0x08)
#define MCPWM0_TH11        REG32(MCPWM0_BASE + 0x0C)
#define MCPWM0_TH20        REG32(MCPWM0_BASE + 0x10)
#define MCPWM0_TH21        REG32(MCPWM0_BASE + 0x14)
#define MCPWM0_TH30        REG32(MCPWM0_BASE + 0x18)
#define MCPWM0_TH31        REG32(MCPWM0_BASE + 0x1C)
#define MCPWM0_TH40        REG32(MCPWM0_BASE + 0x20)
#define MCPWM0_TH41        REG32(MCPWM0_BASE + 0x24)
#define MCPWM0_TH50        REG32(MCPWM0_BASE + 0x28)
#define MCPWM0_TH51        REG32(MCPWM0_BASE + 0x2C)
#define MCPWM0_TMR0        REG32(MCPWM0_BASE + 0x30)
#define MCPWM0_TMR1        REG32(MCPWM0_BASE + 0x34)
#define MCPWM0_TMR2        REG32(MCPWM0_BASE + 0x38)
#define MCPWM0_TMR3        REG32(MCPWM0_BASE + 0x3C)
#define MCPWM0_TH0          REG32(MCPWM0_BASE + 0x40)
#define MCPWM0_TH1          REG32(MCPWM0_BASE + 0x44)
#define MCPWM0_CNT0         REG32(MCPWM0_BASE + 0x48)
#define MCPWM0_CNT1         REG32(MCPWM0_BASE + 0x4C)
#define MCPWM0_UPDATE       REG32(MCPWM0_BASE + 0x50)
#define MCPWM0_FCNT         REG32(MCPWM0_BASE + 0x54)
#define MCPWM0_EVT0         REG32(MCPWM0_BASE + 0x58)
#define MCPWM0_EVT1         REG32(MCPWM0_BASE + 0x5C)
#define MCPWM0_DTH00        REG32(MCPWM0_BASE + 0x60)
#define MCPWM0_DTH01        REG32(MCPWM0_BASE + 0x64)
#define MCPWM0_DTH10        REG32(MCPWM0_BASE + 0x68)
#define MCPWM0_DTH11        REG32(MCPWM0_BASE + 0x6C)

#define MCPWM0_FLT          REG32(MCPWM0_BASE + 0x70)
#define MCPWM0_SDCFG        REG32(MCPWM0_BASE + 0x74)
#define MCPWM0_AUEN         REG32(MCPWM0_BASE + 0x78)
#define MCPWM0_TCLK         REG32(MCPWM0_BASE + 0x7C)
#define MCPWM0_IE0          REG32(MCPWM0_BASE + 0x80)
#define MCPWM0_IF0          REG32(MCPWM0_BASE + 0x84)
#define MCPWM0_IE1          REG32(MCPWM0_BASE + 0x88)
#define MCPWM0_IF1          REG32(MCPWM0_BASE + 0x8C)
#define MCPWM0_EIE          REG32(MCPWM0_BASE + 0x90)
#define MCPWM0_EIF          REG32(MCPWM0_BASE + 0x94)
#define MCPWM0_RE           REG32(MCPWM0_BASE + 0x98)
#define MCPWM0_PP           REG32(MCPWM0_BASE + 0x9C)
#define MCPWM0_IO01         REG32(MCPWM0_BASE + 0xA0)
#define MCPWM0_IO23         REG32(MCPWM0_BASE + 0xA4)
#define MCPWM0_IO45         REG32(MCPWM0_BASE + 0xA8)

#define MCPWM0_FAIL012      REG32(MCPWM0_BASE + 0xB0)
#define MCPWM0_FAIL345      REG32(MCPWM0_BASE + 0xB4)
#define MCPWM0_CH_DEF       REG32(MCPWM0_BASE + 0xB8)
#define MCPWM0_CH_MASK      REG32(MCPWM0_BASE + 0xBC)
#define MCPWM0_PRT          REG32(MCPWM0_BASE + 0xC0)
#define MCPWM0_SWAP         REG32(MCPWM0_BASE + 0xC4)
#define MCPWM0_STT_HYST     REG32(MCPWM0_BASE + 0xC8)
#define MCPWM0_ZCS_DELAY    REG32(MCPWM0_BASE + 0xCC)


#define GPIO0_PIE           REG32(GPIO0_BASE + 0x00)
#define GPIO0_POE           REG32(GPIO0_BASE + 0x04)
#define GPIO0_PDI           REG32(GPIO0_BASE + 0x08)
#define GPIO0_PDO           REG32(GPIO0_BASE + 0x0C)
#define GPIO0_PUE           REG32(GPIO0_BASE + 0x10)
#define GPIO0_PODE          REG32(GPIO0_BASE + 0x18)
#define GPIO0_PFLT          REG32(GPIO0_BASE + 0x1C)
#define GPIO0_F3210         REG32(GPIO0_BASE + 0x20)
#define GPIO0_F7654         REG32(GPIO0_BASE + 0x24)
#define GPIO0_FBA98         REG32(GPIO0_BASE + 0x28)
#define GPIO0_FFEDC         REG32(GPIO0_BASE + 0x2C)
#define GPIO0_BSRR          REG32(GPIO0_BASE + 0x30)
#define GPIO0_BRR           REG32(GPIO0_BASE + 0x34)


#define GPIO1_PIE           REG32(GPIO1_BASE + 0x00)
#define GPIO1_POE           REG32(GPIO1_BASE + 0x04)
#define GPIO1_PDI           REG32(GPIO1_BASE + 0x08)
#define GPIO1_PDO           REG32(GPIO1_BASE + 0x0C)
#define GPIO1_PUE           REG32(GPIO1_BASE + 0x10)
#define GPIO1_PODE          REG32(GPIO1_BASE + 0x18)
#define GPIO1_PFLT          REG32(GPIO1_BASE + 0x1C)
#define GPIO1_F3210         REG32(GPIO1_BASE + 0x20)
#define GPIO1_F7654         REG32(GPIO1_BASE + 0x24)
#define GPIO1_FBA98         REG32(GPIO1_BASE + 0x28)
#define GPIO1_FFEDC         REG32(GPIO1_BASE + 0x2C)
#define GPIO1_BSRR          REG32(GPIO1_BASE + 0x30)
#define GPIO1_BRR           REG32(GPIO1_BASE + 0x34)


#define GPIO2_PIE           REG32(GPIO2_BASE + 0x00)
#define GPIO2_POE           REG32(GPIO2_BASE + 0x04)
#define GPIO2_PDI           REG32(GPIO2_BASE + 0x08)
#define GPIO2_PDO           REG32(GPIO2_BASE + 0x0C)
#define GPIO2_PUE           REG32(GPIO2_BASE + 0x10)
#define GPIO2_PODE          REG32(GPIO2_BASE + 0x18)
#define GPIO2_PFLT          REG32(GPIO2_BASE + 0x1C)
#define GPIO2_F3210         REG32(GPIO2_BASE + 0x20)
#define GPIO2_F7654         REG32(GPIO2_BASE + 0x24)
#define GPIO2_FBA98         REG32(GPIO2_BASE + 0x28)
#define GPIO2_FFEDC         REG32(GPIO2_BASE + 0x2C)
#define GPIO2_BSRR          REG32(GPIO2_BASE + 0x30)
#define GPIO2_BRR           REG32(GPIO2_BASE + 0x34)


#define GPIO3_PIE           REG32(GPIO3_BASE + 0x00)
#define GPIO3_POE           REG32(GPIO3_BASE + 0x04)
#define GPIO3_PDI           REG32(GPIO3_BASE + 0x08)
#define GPIO3_PDO           REG32(GPIO3_BASE + 0x0C)
#define GPIO3_PUE           REG32(GPIO3_BASE + 0x10)
#define GPIO3_PODE          REG32(GPIO3_BASE + 0x18)
#define GPIO3_PFLT          REG32(GPIO3_BASE + 0x1C)
#define GPIO3_F3210         REG32(GPIO3_BASE + 0x20)
#define GPIO3_F7654         REG32(GPIO3_BASE + 0x24)
#define GPIO3_FBA98         REG32(GPIO3_BASE + 0x28)
#define GPIO3_FFEDC         REG32(GPIO3_BASE + 0x2C)
#define GPIO3_BSRR          REG32(GPIO3_BASE + 0x30)
#define GPIO3_BRR           REG32(GPIO3_BASE + 0x34)


#define EXTI_CR0            REG32(EXTI_BASE  + 0x00)
#define EXTI_CR1            REG32(EXTI_BASE  + 0x04)
#define EXTI_IE             REG32(EXTI_BASE  + 0x08)
#define EXTI_IF             REG32(EXTI_BASE  + 0x0C)
#define CLKO_SEL            REG32(EXTI_BASE  + 0x10)
#define PWM_SWAP            REG32(EXTI_BASE  + 0x14)

#define CRC0_DR             REG32(CRC0_BASE  + 0x00)
#define CRC0_CR             REG32(CRC0_BASE  + 0x04)
#define CRC0_INIT           REG32(CRC0_BASE  + 0x08)
#define CRC0_POL            REG32(CRC0_BASE  + 0x0C)

#define UART0_CTRL          REG32(UART0_BASE + 0x00) 
#define UART0_DIVH          REG32(UART0_BASE + 0x04)
#define UART0_DIVL          REG32(UART0_BASE + 0x08)
#define UART0_BUFF          REG32(UART0_BASE + 0x0C)
#define UART0_ADR           REG32(UART0_BASE + 0x10)
#define UART0_STT           REG32(UART0_BASE + 0x14)
#define UART0_RE            REG32(UART0_BASE + 0x18)
#define UART0_IE            REG32(UART0_BASE + 0x1C)
#define UART0_IF            REG32(UART0_BASE + 0x20)
#define UART0_IOC           REG32(UART0_BASE + 0x24)

#define UART1_CTRL          REG32(UART1_BASE + 0x00) 
#define UART1_DIVH          REG32(UART1_BASE + 0x04)
#define UART1_DIVL          REG32(UART1_BASE + 0x08)
#define UART1_BUFF          REG32(UART1_BASE + 0x0C)
#define UART1_ADR           REG32(UART1_BASE + 0x10)
#define UART1_STT           REG32(UART1_BASE + 0x14)
#define UART1_RE            REG32(UART1_BASE + 0x18)
#define UART1_IE            REG32(UART1_BASE + 0x1C)
#define UART1_IF            REG32(UART1_BASE + 0x20)
#define UART1_IOC           REG32(UART1_BASE + 0x24)


#define DMA0_CCR0           REG32(DMA0_BASE + 0x00)
#define DMA0_REN0           REG32(DMA0_BASE + 0x04)
#define DMA0_CTMS0          REG32(DMA0_BASE + 0x08)
#define DMA0_SADR0          REG32(DMA0_BASE + 0x0C)
#define DMA0_DADR0          REG32(DMA0_BASE + 0x10)

#define DMA0_CCR1           REG32(DMA0_BASE + 0x20)
#define DMA0_REN1           REG32(DMA0_BASE + 0x24)
#define DMA0_CTMS1          REG32(DMA0_BASE + 0x28)
#define DMA0_SADR1          REG32(DMA0_BASE + 0x2C)
#define DMA0_DADR1          REG32(DMA0_BASE + 0x30)

#define DMA0_CCR2           REG32(DMA0_BASE + 0x40)
#define DMA0_REN2           REG32(DMA0_BASE + 0x44)
#define DMA0_CTMS2          REG32(DMA0_BASE + 0x48)
#define DMA0_SADR2          REG32(DMA0_BASE + 0x4C)
#define DMA0_DADR2          REG32(DMA0_BASE + 0x50)

#define DMA0_CCR3           REG32(DMA0_BASE + 0x60)
#define DMA0_REN3           REG32(DMA0_BASE + 0x64)
#define DMA0_CTMS3          REG32(DMA0_BASE + 0x68)
#define DMA0_SADR3          REG32(DMA0_BASE + 0x6C)
#define DMA0_DADR3          REG32(DMA0_BASE + 0x70)

#define DMA0_CTRL           REG32(DMA0_BASE + 0x80)
#define DMA0_IE             REG32(DMA0_BASE + 0x84)
#define DMA0_IF             REG32(DMA0_BASE + 0x88)


#define CAN_RBUF_00         REG32(CAN0_BASE + 0x0000)
#define CAN_RBUF_01         REG32(CAN0_BASE + 0x0004)
#define CAN_RBUF_02         REG32(CAN0_BASE + 0x0008)
#define CAN_RBUF_03         REG32(CAN0_BASE + 0x000C)

#define CAN_RBUF0           REG32(CAN0_BASE + 0x0000)
#define CAN_RBUF1           REG32(CAN0_BASE + 0x0004)
#define CAN_RBUF2           REG32(CAN0_BASE + 0x0008)
#define CAN_RBUF3           REG32(CAN0_BASE + 0x000C)

#define CAN_TBUF_00         REG32(CAN0_BASE + 0x0050)
#define CAN_TBUF_01         REG32(CAN0_BASE + 0x0054)
#define CAN_TBUF_02         REG32(CAN0_BASE + 0x0058)
#define CAN_TBUF_03         REG32(CAN0_BASE + 0x005C)

#define CAN_TBUF0           REG32(CAN0_BASE + 0x0050)
#define CAN_TBUF1           REG32(CAN0_BASE + 0x0054)
#define CAN_TBUF2           REG32(CAN0_BASE + 0x0058)
#define CAN_TBUF3           REG32(CAN0_BASE + 0x005C)

#define CAN_CFG_STAT        REG8(CAN0_BASE  + 0x00A0)
#define CAN_TCMD            REG8(CAN0_BASE  + 0x00A1)
#define CAN_TCTRL           REG8(CAN0_BASE  + 0x00A2)
#define CAN_RCTRL           REG8(CAN0_BASE  + 0x00A3)

#define CAN_RTIE            REG8(CAN0_BASE  + 0x00A4)
#define CAN_RTIF            REG8(CAN0_BASE  + 0x00A5)
#define CAN_ERRINT          REG8(CAN0_BASE  + 0x00A6)
#define CAN_LIMIT           REG8(CAN0_BASE  + 0x00A7)
#define CAN_SBAUD           REG32(CAN0_BASE + 0x00A8)

#define CAN_EALCAP          REG8(CAN0_BASE  + 0x00B0)

#define CAN_RECNT           REG8(CAN0_BASE  + 0x00B2)
#define CAN_TECNT           REG8(CAN0_BASE  + 0x00B3)
#define CAN_ACFCTRL         REG8(CAN0_BASE  + 0x00B4)

#define CAN_ACFEN           REG16(CAN0_BASE + 0x00B6)
#define CAN_ACF             REG32(CAN0_BASE + 0x00B8)//same address has different meaning


#define SIF0_CFG            REG32(SIF0_BASE + 0x00)
#define SIF0_TOSC           REG32(SIF0_BASE + 0x04)
#define SIF0_TSTH1          REG32(SIF0_BASE + 0x08)
#define SIF0_TDTH1          REG32(SIF0_BASE + 0x0C)
#define SIF0_IRQ            REG32(SIF0_BASE + 0x10)
#define SIF0_WDATA          REG32(SIF0_BASE + 0x14)

#define IWDG_PSW            REG32(IWDG_BASE + 0x00)
#define IWDG_CFG            REG32(IWDG_BASE + 0x04)
#define IWDG_CLR            REG32(IWDG_BASE + 0x08)
#define IWDG_WTH            REG32(IWDG_BASE + 0x0C)
#define IWDG_RTH            REG32(IWDG_BASE + 0x10)
#define IWDG_CNT            REG32(IWDG_BASE + 0x14)
#define PSW_IWDG_PRE        0xA6B4
#define PSW_IWDG_CLR        0x798D

#define AON_PWR_CFG         REG32(AON_BASE + 0x00)
#define AON_EVT_RCD         REG32(AON_BASE + 0x04)
#define AON_IO_WAKE_POL     REG32(AON_BASE + 0x08)
#define AON_IO_WAKE_EN      REG32(AON_BASE + 0x0C)
#define PSW_EVT_CLR         0xCA40

#define DSP0_SC             REG32(DSP0_REG_BASE + 0x00)
#define DSP0_THETA          REG32(DSP0_REG_BASE + 0x04)
#define DSP0_X              REG32(DSP0_REG_BASE + 0x08)
#define DSP0_Y              REG32(DSP0_REG_BASE + 0x0C)
#define DSP0_SIN            REG32(DSP0_REG_BASE + 0x10)
#define DSP0_COS            REG32(DSP0_REG_BASE + 0x14)
#define DSP0_MOD            REG32(DSP0_REG_BASE + 0x18)
#define DSP0_ARCTAN         REG32(DSP0_REG_BASE + 0x1C)
#define DSP0_DID            REG32(DSP0_REG_BASE + 0x20)
#define DSP0_DIS            REG32(DSP0_REG_BASE + 0x24)
#define DSP0_QUO            REG32(DSP0_REG_BASE + 0x28)
#define DSP0_REM            REG32(DSP0_REG_BASE + 0x2C)
#define DSP0_RAD            REG32(DSP0_REG_BASE + 0x30)
#define DSP0_SQRT           REG32(DSP0_REG_BASE + 0x34)
#define DSP0_PC             REG32(DSP0_REG_BASE + 0x38)

// CL0
#define CL0_EN0             REG32(CL0_BASE + 0x00)
#define CL0_IE0             REG32(CL0_BASE + 0x04)
#define CL0_IF0             REG32(CL0_BASE + 0x08)
#define CL0_OUT0            REG32(CL0_BASE + 0x0C)
#define CL0_MX0             REG32(CL0_BASE + 0x10)
#define CL0_FN0             REG32(CL0_BASE + 0x14)
#define CL0_CF0             REG32(CL0_BASE + 0x18)


// SYS_CLK_FEN
#define MCLK_RCG_B_SPI0      0
#define MCLK_RCG_B_I2C0      1
#define MCLK_RCG_B_CMP       2
#define MCLK_RCG_B_HALL0     3

#define MCLK_RCG_B_TIMER0    4
#define MCLK_RCG_B_TIMER1    5
#define MCLK_RCG_B_TIMER2    6
#define MCLK_RCG_B_TIMER3    7

#define MCLK_RCG_B_QEP0      8
#define MCLK_RCG_B_QEP1      9
#define MCLK_RCG_B_MCPWM0    10
#define MCLK_RCG_B_GPIO      11

#define MCLK_RCG_B_ADC0      12
#define MCLK_RCG_B_ADC1      13
#define MCLK_RCG_B_UART0     14
#define MCLK_RCG_B_UART1     15

#define MCLK_RCG_B_CRC0      16
#define MCLK_RCG_B_DSP0      17
#define MCLK_RCG_B_DMA0      18
#define MCLK_RCG_B_CAN0      19
#define MCLK_RCG_B_SIF0      20
#define MCLK_RCG_B_CLU0      21

#ifdef __cplusplus
}
#endif

#endif /* LKS32MC07X_H */

#include <core_cm0.h>

/** @} */ /* End of group LKS32MC07x */

/** @} */ /* End of group Linko Ltd. */
